How Is FinFET Technology Changing the Meaning of Chip Sign-Off?
Modern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices. Learn more.
Comprehensive Layout-Based On-Chip and Chip-Package-System ESD Sign-off Solution Tutorial
If you are attending the 2014 EOS/ESD Symposium in Tucson, U.S.A. consider registering for this informative tutorial session on September 11. And, don't miss ANSYS papers at the EOS/ESD Electronic Design Automation session on September 10. |
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Structural Tech Tip: Leveraging Parametric CAD Models with ANSYS Bidirectional Interfaces
Existing native CAD geometry can be used for simulation directly, without translation. In addition, ANSYS Workbench also imports additional attributes such as materials, selections of entities and more importantly the design parameters.
ANSYS Comprehensive Solutions for Advanced Materials
Complex systems require innovative use of materials. Composite systems simulation can be time consuming without dedicated solutions so ANSYS had developed an intuitive efficient process for simulating composite systems. |